搜索资源列表
canbus
- CAN总线的FPGA实现,用Verilog编写,代码完整,而且有很完善的测试代码,用ISE直接打开,学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
mult
- 32位浮点乘法器的源代码,用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
divider
- verilog HDL编写的浮点除法器,编译通过,可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
fpadd
- 利用verilog hdl编写的浮点加法器运算单元,单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
undistort
- floating point arthematic function with verilog code
Nand_verilog
- NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors VT) is the bit line pulled low.
69491706fp_add_sub
- verilog code for floating point adding
fpu100_latest.tar
- 这是一个32位的浮点运算单元(FPU),它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
floating_point_addition_subtraction
- Simple floating point addition unit written in Verilog
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
CourseDesign
- 用Verilog实现一位原码浮点数乘法器,按照累加的方式,逐位相乘,再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
fpufiles
- floating point adder mul and sub in verilog code
fpu_div
- verilog code floating point division
floating-point-adder
- verilog implementation of the floating point adder
floating-point-multiplier
- verilog implementation of the floating point multiplier
FPU
- Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
数字信号处理的FPGA实现-第三版-verilog源程序
- 数字信号处理的FPGA实现, 包括了FPGA基础知识,浮点运算,信号处理的FIR FFT等,附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
subtraction floating point
- subtract two number floating point (32 bit)
eetop.cn_利用FPGA实现浮点运算的verilog代码
- 计算机里整数和小数形式就是按普通格式进行存储,例如1024、3.1415926等等,这个没什么特点,但是这样的数精度不高,表达也不够全面,为了能够有一种数的通用表示法,就发明了浮点数。 浮点数的表示形式有点像科学计数法(*.*****×10^***),它的表示形式是0.*****×10^***,在计算机中的形式为 .***** e ±***),其中前面的星号代表定点小数,也就是整数部分为0的纯小数,后面的指数部分是定点整数。利用这样的形式就能表示出任意一个整数和小数,例如1024就能表示成0.
Fixed-Floating-Point-Adder-Multiplier-master
- Fixed-Floating-Point-Adder-Multiplier with test bench